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Master/DMA Parameters
If a memory or I/O BAR is used for the DMA registers (DMA_REG_LOC set to 2 or 3, Table 4-4 ), the BAR specified
by DMA_REG_BAR ( Table 4-4 ) should be configured as follows:
BAR i _ENABLE = 1
BAR i _ADDR_WIDTH = 8
BAR i _IS_IO = 0 (memory BAR) or 1 (I/O BAR)
BAR i _PREFETCH = 0
This BAR will be used solely to access the DMA control registers and configuration space. It cannot be used to access
user logic connected to the backend of the core.
Master/DMA Parameters
Table 4-4 · Master/DMA Parameters
Name
BACKEND
DMA_REG_LOC
DMA_REG_BAR
DMA_COUNT_WIDTH
ENABLE_DIRECTDMA
Values
0 or 1
0 to 3
0 to 5
8 to 32
0 or 1
Description
When 1, the backend interface to the DMA control registers is enabled. When 0, the DMA
registers can only be accessed from the PCI bus.
If BACKEND = 1 and DMA_REG_LOC > 0, the DMA control registers can be accessed from
both the PCI and backend interfaces.
Configures how the DMA control registers are accessed from the PCI bus.
0: None – DMA registers can be read at locations 50-5F hex of the configuration space, but not
written. Register read/writes are expected to be from the backend interface. (The BACKEND
parameter must be set to 1 for backend access.)
1: Config – DMA registers are mapped to locations 50–5F hex of the configuration space.
2: MEM – DMA registers are mapped to configuration space and memory locations 50–5F hex
of the BAR set by DMA_REG_BAR.
3: I/O – DMA registers are mapped to configuration space and I/O locations 50–5F hex of the
BAR set by DMA_REG_BAR.
Sets which BAR is used to access the DMA registers if DMA_REG_LOC is set to 2 or 3. The
BAR parameters must be set up to configure a 256-byte BAR, either memory- or I/O-mapped
with prefetch disabled. This BAR is in addition to other memory and I/O BARs being used. In
other words, the BAR used for DMA registers may not be shared with other memory and I/O
BARs used to access user logic connected to the core.
Sets the width of the internal DMA counter. For example, if DMA_COUNT_WIDTH is set
to 12, the DMA engine can transfer up to 4,096 bytes of data.
Max Transfer Size = 2 DMA_COUNT_WIDTH
Enables core support for direct DMA operations.
When 1, direct DMA mode is enabled, allowing the PCI data value to be read from and written
to an internal register rather than the backend interface.
v4.0
39
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